The present invention is directed to input-output (IO) devices, and especially to serializer/deserializer (SERDES) devices. Analog SERDES modules operating at high speeds may experience a problem in controlling the tri-state output device of the SERDES module with sufficient accuracy to meet standards requirements that establish constraints more stringent than the slower clock period of digital control circuitry that controls the SERDES module. A solution to this problem in the past has been to operate the digital control circuitry of the SERDES module at a high speed in order to meet requirements.
There are disadvantages to such high speed operation of the digital control circuitry of the SERDES module including, by way of example and not by way of limitation, higher power consumption, increased difficulty in maintaining timing, more expensive parts for handling higher speed technology and more complex logic in the data path.
There is a need for a system and method for presenting serial drive signals for effecting communication of a plurality parallel data signals that permits operation of digital control circuitry at a speed less than the output speed of the module.
There is a need for a serializer/deserializer (SERDES) module that may operate control circuitry at a lower speed than the operational speed of output signals from the module.